Illegal opcodes:

Opcode

imp

imm

zp

zpx

zpy

izx

izy

abs

abx

aby

ind

rel

Function

N

V

B

D

I

Z

C

SLO

$07

$17

$03

$13

$0F

$1F

$1B

{adr}:={adr}*2 A:=A or {adr}

*

*

*

RLA

$27

$37

$23

$33

$2F

$3F

$3B

{adr}:={adr}rol A:=A and {adr}

*

*

*

SRE

$47

$57

$43

$53

$4F

$5F

$5B

{adr}:={adr}/2 A:=A exor {adr}

*

*

*

RRA

$67

$77

$63

$73

$6F

$7F

$7B

{adr}:={adr}ror A:=A adc {adr}

*

*

*

*

SAX

$87

$97

$83

$8F

{adr}:=A&X

LAX

$A7

$B7

$A3

$B3

$AF

$BF

A,X:={adr}

*

*

DCP

$C7

$D7

$C3

$D3

$CF

$DF

$DB

{adr}:={adr}-1 A-{adr}

*

*

*

ISC

$E7

$F7

$E3

$F3

$EF

$FF

$FB

{adr}:={adr}+1 A:=A-{adr}

*

*

*

*

ANC

$0B

A:=A&#{imm}

*

*

*

ANC

$2B

A:=A&#{imm}

*

*

*

ALR

$4B

A:=(A&#{imm})/2

*

*

*

ARR

$6B

A:=(A&#{imm})/2

*

*

*

*

XAA²

$8B

A:=X&#{imm}

*

*

LAX²

$AB

A,X:=#{imm}

*

*

AXS

$CB

X:=A&X-#{imm}

*

*

*

SBC

$EB

A:=A-#{imm}

*

*

*

*

AHX¹

$93

$9F

{adr}:=A&X&H

SHY¹

$9C

{adr}:=Y&H

SHX¹

$9E

{adr}:=X&H

TAS¹

$9B

S:=A&X {adr}:=S&H

LAS

$BB

A,X,S:={adr}&S

*

*

imm = #$00
zp = $00
zpx = $00,X
zpy = $00,Y
izx = ($00,X)
izy = ($00),Y
abs = $0000
abx = $0000,X
aby = $0000,Y
ind = ($0000)
rel = $0000 (PC-relative)



¹ = unstable in certain matters
² = highly unstable (results are not predictable on some machines)
A = Akkumulator
X = X-Register
Y = Y-Register
S = Stack-Pointer
P = Status-Register
+(S) = Stack-Pointer relative with pre-increment
(S)- = Stack-Pointer relative with post-decrement


Combinations of two operations with the same addressing mode:

SLO {adr} = ASL {adr} + ORA {adr}
RLA {adr} = ROL {adr} + AND {adr}
SRE {adr} = LSR {adr} + EOR {adr}
RRA {adr} = ROR {adr} + ADC {adr}
SAX {adr} = store A&X into {adr}
LAX {adr} = LDA {adr} + LDX {adr}
DCP {adr} = DEC {adr} + CMP {adr}
ISC {adr} = INC {adr} + SBC {adr}

note to SAX: the A&X operation is a result of A and X put onto the bus at the same time.


Combinations of an immediate and an implied command:

ANC #{imm} = AND #{imm} + (ASL)
ANC #{imm} = AND #{imm} + (ROL)
ALR #{imm} = AND #{imm} + LSR
ARR #{imm} = AND #{imm} + ROR
XAA #{imm} = TXA + AND #{imm}
LAX #{imm} = LDA #{imm} + TAX
AXS #{imm} = A&X minus #{imm} into X
SBC #{imm} = SBC #{imm} + NOP

note to ANC: this command performs an AND operation only, but bit 7 is put into the carry, as if the ASL/ROL would have been executed.
note to ARR: part of this command are some ADC mechanisms. following effects appear after AND but before ROR: the V-Flag is set according to (A and #{imm})+#{imm}, bit 0 does NOT go into carry, but bit 7 is exchanged with the carry.
note to XAA: DO NOT USE!!! Highly unstable!!!
note to LAX: DO NOT USE!!! On my C128, this opcode is stable, but on my C64-II it loses bits so that the operation looks like this: ORA #? AND #{imm} TAX.
note to AXS: performs CMP and DEX at the same time, so that the MINUS sets the flag like CMP, not SBC.


Combinations of STA/STX/STY:

AHX {adr} = stores A&X&H into {adr}
SHX {adr} = stores X&H into {adr}
SHY {adr} = stores Y&H into {adr}

note: sometimes the &H drops off. Also page boundary crossing will not work as expected (the bank where the value is stored may be equal to the value stored).


Combinations of STA/TXS and LDA/TSX:

TAS {adr} = stores A&X into S and A&X&H into {adr}
LAS {adr} = stores {adr}&S into A, X and S

note to LAS: is called as "propably unreliable" in one source.


Bit configuration does not allow any operation on these ones:

NOP = has no effects
NOP #{imm} = fetches #{imm} but has no effects
NOP {adr} = fetches {adr} but has no effects


KIL = halts the CPU. the data bus will be set to #$FF


Aliases used in other illegal opcode sources:

SLO = ASO
SRE = LSE
ISC = ISB
ALR = ASR
SHX = A11 (A11 was a result of only having tested this one on adress $1000)
SHY = A11
LAS = LAR
KIL = JAM, HLT


Linky